Re: Deskew Reginal clock input
On Nov 24, 12:31*pm, bonnerfme <xiaoling...@fme.fujitsu.com> wrote:
> On Nov 24, 2:49*pm, Gabor <ga...@alacron.com> wrote:
>
>
>
> > On Nov 24, 8:07*am, bonnerfme <xiaoling...@fme.fujitsu.com> wrote:
>
> > > Hi there,
>
> > > I have a question regarding clock deskewing. My design has a sub
> > > module that gets its clock signal from a regional clock pin, however,
> > > the clock skew is too large and causing timing violations.
>
> > > I read about something on DCM and thought about using it to deskew
> > > this regional clock, but it seems to me that DCM can only be used in
> > > conjunction with global clock lines. The board layout is fixed, which
> > > means no way I can use a global clock line for this signal, have to
> > > live with it.
>
> > > Has anybody experience with regional clock deskewing?
>
> > > Thanks a lot!
>
> > Are you sure you mean deskew? *That is a routing issue. *I don't
> > see how a DCM would help unless you're talking about the skew
> > between the regional clock and some other clock.
>
> > Confused,
> > Gabor
>
> Hi Gabor, you're right, this is a routing issue.I meant the skew just
> on this regional clock, not the skew between it and some other clock.
> Maybe DCM is not the right thing to go for, I'm no sure, please advise
> what is the correct thing I should look into.
>
> BR
What kind of device are you using? Is this "Regional clock"
driven by a dedicated clock buffer like a BUFR in the Virtex 5?
Or do you mean you're using non-global routing resources for
the clock?
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