input violations, output violations, or flop/flop violations?

Is your clock being routed using logic routing resources or a dedicated
clock resource? Your clock needs to go on a global clock line if it isn't
there already. It's hard to meet timing with clocks on logic routing, maybe
with some careful hand placement you could do it.

--steve

"bonnerfme" <[email protected]> wrote in message
news:[email protected]...
: Hi there,
:
: I have a question regarding clock deskewing. My design has a sub
: module that gets its clock signal from a regional clock pin, however,
: the clock skew is too large and causing timing violations.
:
: I read about something on DCM and thought about using it to deskew
: this regional clock, but it seems to me that DCM can only be used in
: conjunction with global clock lines. The board layout is fixed, which
: means no way I can use a global clock line for this signal, have to
: live with it.
:
: Has anybody experience with regional clock deskewing?
:
: Thanks a lot!