On Sat, 21 Nov 2009, Antti wrote:

> On Nov 21, 11:34*pm, Sam Kerr <stk...@purdue.edu> wrote:
> > Hello all,
> >
> > I'm trying to implement a ring oscillator using 1 nand gate connected to a
> > series of not gates. Synthesis produces no relevant warnings, but
> > translation says all the wires are source-less and is removing them,
> > despite settings I have provided through constraints.
> >
> > In the ISE map options, I have checked "Register Duplication" as well as
> > adding a Keep constraint in the verilog source, which is below.
> >
> > Here is an example of some of the messages I'm seeing:
> >
> > The signal "puf1/mux2/N1" is sourceless and has been removed.
> > The signal "puf1/mux2/N2" is sourceless and has been removed.
> > The signal "puf1/mux1/N1" is sourceless and has been removed.
> > The signal "puf1/mux1/N2" is sourceless and has been removed.
> > The signal "puf1/oscillator1/N0" is sourceless and has been removed.
> > The signal "puf1/oscillator1/N1" is sourceless and has been removed.
> > The signal "puf1/oscillator1/inputGate/N1" is sourceless and has been removed.
> > The signal "puf1/oscillator1/inputGate/N2" is sourceless and has been removed.
> > The signal "puf1/oscillator1/GATELOOP[35]..endGate/N1" is sourceless and has been removed.
> > The signal "puf1/oscillator1/GATELOOP[35]..endGate/N2" is sourceless and has been removed.
> > The signal "puf1/oscillator1/GATELOOP[35].gate/N1" is sourceless and has been removed.
> > The signal "puf1/oscillator1/GATELOOP[35].gate/N2" is sourceless and has been removed.
> > The signal "puf1/oscillator1/GATELOOP[34].gate/N1" is sourceless and has been removed.
> > The signal "puf1/oscillator1/GATELOOP[34].gate/N2" is sourceless and has been removed.
> > ...
> >
> > What is also interesting, is my Verilog source does not define an N1 orN2
> > signal, and I can't figure out what these correspond to.
> >
> > Here is the Verilog code I'm using.
> >
> > module ringoscillator(
> > output wire out
> > );
> >
> > (* KEEP = "TRUE" *) wire connector;
> > (* KEEP = "TRUE" *) wire [36:0] w;
> >
> > nandgate inputGate(.i1(connector), .i2(1'b1), .out(w[0]));
> >
> > // generate inverters
> > genvar i;
> >
> > generate
> > * *for(i = 0; i < 36; i = i + 1)
> > * *begin : GATELOOP
> > * * * * invertergate gate(.in(w[i]), .out(w[i+1]));
> > * * * * if(i+1 == 36)
> > * * * * invertergate endGate(.in(w[i+1]), .out(connector));
> > * *end
> > endgenerate
> >
> > assign out = connector;
> >
> > endmodule
> >
> > module nandgate(input wire i1, i2, output wire out);
> > * * * * assign out = ~(i1 & i2);
> > endmodule
> >
> > module invertergate(input wire in, output wire out);
> > * * * * assign out = ~in;
> > endmodule
> >
> > Are there any flaws in the code or settings I can make to stop ISE fromremoving my logic?
> >
> > Thanks for any help!
>
> WHY SO COMPLICATED??
>
> just take xilinx own ring oscillator code, it works
> (one place is s3e sk ref designs, freq measurement example)
>
> Antti
>


Thanks for this advice, where can I find these designs?