On Nov 12, 11:20*am, Didi <d...@tgi-sci.com> wrote:
>
> That is true, it does seem to work. On the 6.3 version, at least.
> The end result I get does go through that conversion as well, I
> can see that during compilation, the vhdl source is also visible
> I think.
>
> What does seem not to work in the 11 thing is some higher level
> automation, they don't bother parsing the Abel source for pin
> assignments and endup without any (my assumption only, could
> be anything else).

By default I think it auto-fits (floats the pins), but if you click
Lock Pins, you get a .UCF for that fit pass, and can then move the
pins about in that file.

Usually I let the fitter have first pass, and create the reports etc,
and then I start worrying about the pins.
It's also good to get design thru the hoops once, before starting to
nail things down..

Not extracting that info from ABEL is rather lazy of Xilinx - that's
really intern level stuff, perhaps they don't sell that many PLDs into
long design life projects ?
Still, a generated UCF file looks simple enough..
-jg