On Nov 12, 11:31*am, Gabor <ga...@alacron.com> wrote:
> I don't think Xilinx ever
> had a version that would allow top-level code in Abel,
> but I could be wrong on that because most of my designs
> are FPGA based rather than CPLD where top-level Abel
> would make sense. *

The ABEL examples I have here, do not need to have SCH top levels.
( I think one does, to show how it can be done..)
-jg