On Nov 11, 11:59*pm, -jg <jim.granvi...@gmail.com> wrote:
> ...
> I was told by a friend a couple of years back, that was how Xilinx
> handled his abel - it did VHDL spins, but they were 'hidden', and it
> took Xilinx a few months to knock the edges off that change, but it
> DID sound like it all worked.

That is true, it does seem to work. On the 6.3 version, at least.
The end result I get does go through that conversion as well, I
can see that during compilation, the vhdl source is also visible
I think.

What does seem not to work in the 11 thing is some higher level
automation, they don't bother parsing the Abel source for pin
assignments and endup without any (my assumption only, could
be anything else).

Dimiter

------------------------------------------------------
Dimiter Popoff Transgalactic Instruments

http://www.tgi-sci.com
------------------------------------------------------
http://www.flickr.com/photos/didi_tg...7600228621276/

Original message: http://groups.google.com/group/comp....8?dmode=source