On Nov 11, 7:24*pm, -jg <jim.granvi...@gmail.com> wrote:
> On Nov 11, 5:43*pm, Didi <d...@tgi-sci.com> wrote:
>
> > I will of course still welcome all help, I am still far from
> > done with this.
>
> > Dimiter
>
> I have a handful of ABL files on a Xilinx stub here, I can compile
> those and zip the results if you give an email ?
>
> -jg

I've blown the dust off the directory(s), and it barfed on converting
the old projects - but it happily made new ones.
* new Project (name becomes subdir)
* right click add source [select .ABL file]
* double click on device, select XCR3128XL
* click on source
* Double click on Fitter report in process list
* Double click on generate Jtag file in process list

and voila, truckloads of files, but the ones that matter are .rpt,
and
..jed

If I right-click on [fit].properties, I can select HDL equation style,
where you can choose Source/ABEL/Verilog/VHDL, and that's what it uses
in the fitter report files. - select the most readable

This is a legacy tool chain, but Xilinx can't have broken any of this,
on newer versions can they ?!

-jg