On Nov 10, 2:14*pm, Didi <d...@tgi-sci.com> wrote:
> There is some
> ABEL thing, is it usable in a way similar to more sane CPLD tools? (I
> gather it gets translated into vhdl to be processed but I guess I can live
> with that for now).

ABEL is a good tool flow for CPLD, and especially good if you want
to keep close to the JED file.

AFAIK, the Xilinx ABEL flow still works, and as you say, it converts
into spagetti VHDL for the rest of the tool chains, and timing.

Xilinx used to include some .abl source examples - if you search for
..abl, what do you find ?

The fitters can report (.rpt) Boolean Eqns in ABEL format, so you can
correlate that with the source code, and track polarity fuses, and
macrocell config fuses etc.
Those report files also have some fuse-level matrix tables,
that you can use to trace small changes.

What happen in-between you can pretty much ignore

Somewhere in the depths, I think the fitters still swallow PLA files/
BLIF formats, and if you are adept at tools, you could even create an
assembler that output BLIF files for the fitters...

A compact Xilinx CPLD flow would be nice to see

-jg