On Nov 10, 3:14*am, Didi <d...@tgi-sci.com> wrote:
> Some time ago I managed to get (under NDA) the programming info
> from Xilinx so now I can program one of their coolrunners via JTAG
> with my
> toolchain (the CPLD on this design is reprogrammable over the net,
> i.e. the
> board CPU does its JTAG access etc.).
>
> *I am now getting to what should be the easy part - writing the CPLD
> source
> to produce some (very simple) logic in a jedec file, after which I am
> fine.
>
> *I got the current xilinx software, started it under windows and got
> really
> scared.
> *Last time I used a not-in-house written logic compiler tool it was
> the PHDL
> thing for the Philips coolrunner (before I had my tool working). It
> was blindingly
> obvious how to use it and I don't remember having to discover much if
> anything
> about it, I just used it. Did not waste an hour.
>
> *I already wasted a few hours with the new xilinx tool.
>
> *It looks like because I want to hit a nail - and I do know how to use
> a hammer quite
> well - I have to hire a farm of robots so one will drive another to
> the shop
> where they will pick a truck of hammers and bring them back for
> another
> robot to choose the right hammer, then they'l put together a table
> onto
> which the operation will be performed and eventrually the talk robot
> will
> be telling me how to proceed with which hammer so I can hit my nail
> while
> holding my arms to protect me from injuring myself.
> Just terrific.
>
> Can someone please suggest something simpler? Which is my fastest way?
> I am not interested in learning all about their tools, I just want my
> logic
> into a jedec file (normally a 10 minutes' task here for what this is
> with my
> old coolrunner tools, but now I want to use a xcr3128xl part). There
> is some
> ABEL thing, is it usable in a way similar to more sane CPLD tools? (I
> gather
> it gets translated into vhdl to be processed but I guess I can live
> with that for
> now). Or their schematic entry, can it be usable? I wasted an hour
> until I
> **began to** figure out how to assign pins to things (far from having
> mastered
> that yet - not bad for a guy who has written his own toolchains for
> such stuff
> while having to do some reverse enginnering on the way, eh...).
>
> Thanks,
>
> Dimiter
>
> ------------------------------------------------------
> Dimiter Popoff * * * * * * * Transgalactic Instruments
>
> http://www.tgi-sci.com
> ------------------------------------------------------http://www.flickr.com/photos/didi_tgi/sets/72157600228621276/

I wonder
why so complicated..

JTAG info for Xilinx devices is PUBLIC (soso 95%) so no need to get it
under NDA
the jedec bitmap info is not so public, but i did RE it withing a few
days

as of "doing something"
1) use schematic for design entry
2) use the graphical tool to assign pins

it works, you should get leds blinking withing hours

from there go as want, use VHDL or verilog both work ok

Antti