>On Mon, 26 Oct 2009 10:53:23 -0400, Jerry Avins wrote:
>
>> thunder wrote:
>>> Hi
>>>
>>> I have a question regarding Fixed point Arithmetic addition.
>>>
>>> For example, i have two fixed point numbers:
>>>
>>> a = unsigned Q7.8 format (7-bit integer, 8 bit factional). b
unsigned
>>> Q7.8 format ( " " ).
>>>
>>> Now a + b = c, where c is an unsigned Q8.8 result.
>>
>> Then there is overflow, just as two Q15.0 integers and getting a Q16.0
>> sum. (Remember the sign bit.)
>>
>>> Qs: How do I transform c into d, where d is a unsigned Q7.9 result ??
>>
>> You can't. Count the bits. (Remember the sign bit.)
>>
>You can't on a 16-bit machine, but if you're working in an FPGA or custo

>logic a 17-bit type is no problem.

Not entirely true (carry flag), but I'm splitting hairs, since the proble
is misguided. BTW, the OP repeatedly said unsigned, though it may hav
been confusing with repeated references to the MSbit.

There's absolutely no point in switching to 7.9 midstream. 7.8 hold
exactly the same information as 7.9 after *this* operation; the loss is i
the integer part, not the fractional part. Adding two unsigned 15 bi
numbers could probably be achieved with exactly the same opcode, becaus
the result merely has to be interpreted correctly (the same is not true o
multiplication, of course). For this problem, I would use all 16 bits th
whole time, not 15. You then have to choose whether to saturate or wra
around. There may be some processors that support saturation as a
instruction, but I think you'd otherwise have to look at the carry flag
this should be trivial for unsigned addition. To wrap, do nothin
(assuming other constraints don't prevent you from using all 16, els
mask).