Hello Grish,
Well lets see, the electrical length of the blind via you described is roughly 10ps. For PCIe gen 2 the minimum rise/fall time is 30ps so these vias could create impedance mismatches for your channel. I would try and match as close as possible to your trace impedance with sufficient ground via returns. If you are able try and model these vias in the channel with a 3D simulator.
Regards,
-Jory
________________________________
From: Girish Gopi <girish.gopi (AT) datapatterns (DOT) co.in>
To: si-list (AT) freelists (DOT) org
Sent: Saturday, July 11, 2009 7:32:10 AM
Subject: [SI-LIST] PCIe routing
Hi all,
I am having the 20 layer pcb with 3MM thickness , using blind vias from 1 to 10 and 11 to 20 layers.Where 2nd layer using for PCIe(5GB/S) routing , can I know that the via used for PCIe routing from layer 2 to 10 , will it be act as a stub ?Is there any issues?
Thanks in advance
Girish
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