On Jul 2, 10:07 am, Kim Enkovaara <kim.enkova...@iki.fi> wrote:
> Sharanbr wrote:
> > How do I ensure that I have got a fairly accurate pinout (assuming
> > meeting timing is not an issue) when
> > the design is still under development. Do people create dummy FPGA top
> > and use special tools that only
> > check the validity of the pinouts wrt to the selected device?
>
> The most simplistic method is just to create dummy toplevel design,
> and do pinmapping to that file with the help of the tools and manual,
> and run the basic DRC checks.
>
> In bigger designs that is not usually enough. If complex clocking or big
> amount of special blocks (serdes for example) are used I at least
> recommend a toplevel that has clocking structures and the special blocks
> instantiated. That file can be then run with the pinmapping trough the
> normal P&R flow to make sure that it is implementable.
>
> And for good PCB layout the pinmapping has to be loaded into PCB level
> tools (Mentor I/O Designer etc.) and the new pinmapping has to be
> verified again in the P&R flow after each modification.
>
> --Kim

Thanks Everyone.

Would like to know how many times it happens that the pinouts (defined
early in the cycle) have to change after the p&r?
It would assume this would depend on:
1) how aggressive the timings are
2) how accurate was the flow used to define early pinout (as Kim
suggested having top level reset/clocking structures)

Do you agree with the assesement?