On Jul 4, 7:19*am, Brian Drummond <brian_drumm...@btconnect.com>
wrote:
> On Fri, 03 Jul 2009 09:28:49 -0700, Mike Treseler <mtrese...@gmail.com> wrote:
> >MM wrote:
>
> >> Sometimes "recompile all modules" may not work first time if the orderof
> >> compilation has not been set properly.
>
> >With vhdl-mode,
>
> >right-click, Speedbar, Generate Makefile
> >right-click, Speedbar, Make
>
> >does the trick.
>
> because VHDL sources contain all the information necessary to determine the (or
> rather, a ) correct order of compilation, and vhdl-mode simply translatesit.
>
> There is really no excuse for other tools being unable to do the same.
>
> (Mixed language projects may be another matter)
>
> - Brian

The Lattice software has a mode of compiling that evaluates the order
to compile the modules and remembers it for subsequent builds. That
was not an issue with my build. I was just restarting my simulation
before I recompiled.

Rick