On Fri, 03 Jul 2009 16:19:43 +0100, Jonathan Bromley
<[email protected]> wrote:

>On Fri, 3 Jul 2009 18:48:55 +0800, steve wrote:
>
>>It looks like it will not work, after adding in the library , it compiles
>>fine, but as soon as it links up to chipscope....
>>to_slv(xxx)
>>
>>FATAL_ERROR:Xst:Portability/export/Port_Main.h:143:1.17 - This application
>>has discovered an exceptional condition from which it cannot recover.
>
>That'll be a bug, then :-)
>
>I'd guess it's related to the use of a conversion
>function in the port map, which is perfectly legal
>but isn't so commonly used, so maybe has not been
>debugged as thoroughly as one might hope.

Possibly because the Chipscope core is a black box, or something other than
VHDL, so XST doesn't have access to both sides of the port. I have also brought
XST down with port type conversions. Can't remember where; probably connecting
to a memory model only available in Verilog.

>Try using the conversion function to put the value
>onto a new std_logic_vector signal, and then hook
>that signal to the appropriate ports.

Definitely the answer in this case. (More of a headache with an inout port!)

- Brian