On Fri, 03 Jul 2009 09:28:49 -0700, Mike Treseler <mtreseler@gmail.com> wrote:

>MM wrote:
>
>> Sometimes "recompile all modules" may not work first time if the order of
>> compilation has not been set properly.
>
>With vhdl-mode,
>
>right-click, Speedbar, Generate Makefile
>right-click, Speedbar, Make
>
>does the trick.

because VHDL sources contain all the information necessary to determine the (or
rather, a ) correct order of compilation, and vhdl-mode simply translates it.

There is really no excuse for other tools being unable to do the same.

(Mixed language projects may be another matter)

- Brian