On Sat, 4 Jul 2009 06:06:43 +0800, Walter wrote
(in article <[email protected]>):

> Jonathan Bromley escribió:
>> On Fri, 3 Jul 2009 10:44:18 -0700 (PDT), Walter wrote:
>>
>>> where is the "extra" signal ?
>>> TRIG2(x) must be directly connected to FFx;
>>
>> I agree that there is no new hardware.
>>
>> In the original post, steve wrote:
>>
>>> TRIG2(31 downto ????) => fifo_cntl_cs ,
>>
>> In other words, TRIG2() is not a signal in
>> his design; it's a port on the ChipScope
>> instance. So it's impossible to write what
>> you suggested; it's necessary to declare
>> an additional signal, use the three assignments
>> to put the appropriate values on that signal,
>> and then attach that signal to the ChipScope
>> port.
>>
>> Nothing more than that: you need to declare
>> a suitable signal.
>
> I agree, as basic as I forget to mention...
>
> Here a more "complete" simple solution to a simple problem.
>
> ..
> SIGNAL TRIG2 : std_logic_vector(31 DOWNTO 0);
>
>
> ..
> TRIG2(31) <= '1' WHEN fifo_cntl_cs = IDLE ELSE '0';
> TRIG2(30) <= '1' WHEN fifo_cntl_cs = RD_REQ ELSE '0';
> TRIG2(29) <= '1' WHEN fifo_cntl_cs = WR_REQ ELSE '0';
>
> --- IN CHIPSCOPE INSTANCE ---
> ...
> TRIG2 => TRIG2,
> ...
>
> When in trainings I recommend to all write code as simple as possible,
> many times "complex" solutions or no common used structures are poorly
> supported or totally unsupported in one or other synthesis tool.
> I like your solution as generic solution, but if I have a more
> "standard" or low level solution, thinking in the synthesis tool, I take
> it.
>
> Walter.
>

Hi Walter,

just to let you know this was the only solution that worked out finally.

steve