On Sat, 4 Jul 2009 03:44:48 +0800, Jonathan Bromley wrote
(in article <[email protected]>):

> On Fri, 3 Jul 2009 10:44:18 -0700 (PDT), Walter wrote:
>
>> where is the "extra" signal ?
>> TRIG2(x) must be directly connected to FFx;
>
> I agree that there is no new hardware.
>
> In the original post, steve wrote:
>
>> TRIG2(31 downto ????) => fifo_cntl_cs ,
>
> In other words, TRIG2() is not a signal in
> his design; it's a port on the ChipScope
> instance. So it's impossible to write what
> you suggested; it's necessary to declare
> an additional signal, use the three assignments
> to put the appropriate values on that signal,
> and then attach that signal to the ChipScope
> port.
>
> Nothing more than that: you need to declare
> a suitable signal.
>


Yep the chipscope comes in as:

component icon

PORT (
CONTROL0 : INOUT STD_LOGIC_VECTOR(35 DOWNTO 0));

end component;



component ila
PORT (
CONTROL : INOUT STD_LOGIC_VECTOR(35 DOWNTO 0);

CLK : IN STD_LOGIC;

TRIG0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);

TRIG1 : IN STD_LOGIC_VECTOR(15 DOWNTO 0);

TRIG2 : IN STD_LOGIC_VECTOR(23 DOWNTO 0);

TRIG3 : IN STD_LOGIC_VECTOR(31 DOWNTO 0));


end component;

sorry I thought this would be common code , so i did not post it.
This is built using the code generator.

I don't use the data ports, but instead tie my signals to the trigger ports,
so i can use any of them to trigger on.

Steve