On Fri, 3 Jul 2009 22:37:57 +0800, Walter wrote
(in article <h2l545$2v0l$[email protected]>):

> steve escribió:
>>
>> As regards , changing the logic/ optimization, I'm already aware of that.
>> when I try and put my chipscope external to my user_logic and probe
>> internally, sometimes the stuff is accessible , other times it disappears,
>> I
>> keep looking to see if paul Daniels is behind me..
>>
>> Like I say these tools and systems are gash, good job Xilinx would never
>> dare charging for them. ;-)
>>
>
> FPGA and Xilinx software are not easy to drive, as a Porsche, but when
> you know how; you have a good chance to win;
>
> user_logic sound as you are using others cores into your project, correct ?
>
> Walter
>
>
>
Hi walter,

Yep, there is a bit of everything , networking , ppc, PLB, OPB2PLB bridge
buttons & led's for debugging, it is a computer forensics project for my
thesis.


But my main issue was the double/triple clocking of a variable that was only
supposed to clock once on a signal transition. It of course is controlled by
the only signal i could not investigate.

my background is software, and we are really spoiled for tools and debugging
setups, I was actually shocked at how bad and messy the hardware development
kit is. (i might take a look at Altera later)

But your solution has been great, I also filed a webcase with xilinx over the
above problem.

Anyway thanks for helping out a noob.

Steve