On Fri, 03 Jul 2009 15:25:46 -0500, "The Lord of War"
<[email protected]> wrote:

>>"The Lord of War" <[email protected]> wrote in message
>>news:[email protected] om...
>>> eh no for what no for I cant use the sram that is onboard or no I have
>to
>>> do some fancy stuff and calls to be able to use them? and if so what do
>i
>>> need to do?
>>
>>No, the fpga doesn't of itself know about the board. It doesn't know
>about
>>the devices on the board. And it doesn't know the minutiae of operation
>of
>>the devices on the board.
>>
>>As to what to do, it depends on what you're trying to do. An embedded
>system
>>can use the Xilinx EDK to interface with the device, attach it to the
>>peripheral bus, assign it room in the memory space, and build drivers to
>
>>access and control the device from software. For a hardware only
>solution,
>>start with the device's datasheet, and build the interface circuitry in
>the
>>fpga. The "process" you can "call" to work with the device might already
>
>>exist. They're more generally referred to as IP Cores. I expect you'll
>find
>>the required IP Cores in the Xilinx tools.
>>
>>"Fancy stuff" on the fpga is more properly thought of as describing and
>>connecting circuitry. It is not software "calls" using a strange new
>>programming language. I hope you'll find that distinction helpful.
>>
>>
>>
>
>I dont know but maybe (or definitely) you guys are way more advanced than
>me that's why I'm getting nothing, so to be clear I have an fpga board on
>it is the virtex 4 and lots of other chips including an sram module and a
>flash (scan disk) and something called linear flash all this is on the SAME
>board as the FPGA and what I'm trying to do is to use these modules to save
>information temporarily, so I need to save data in the sram (the one
>ONboard) to be able to use later. I'm using VHDL to code my project, and my
>question is; HOW can I use these resources which are on the same board.
>
>please help the declaring big array did not work.
>any tutorials or sample code is greatly appreciated
>
>thanks a lot guys and best of regards

Declaring an array in VHDL uses memory _inside_ the FPGA. You need to use
memory _outside_ the FPGA. Imagine that the SRAM chip is connected to a
microprocessor, instead of a FPGA. The micro and the SRAM chip communicate
via Address lines, Data lines (I/O) and control lines (cs*, we*, rd, wr,
etc). The micro puts out a valid address, and sets the control lines to
read from or write to the SRAM chip. The data travels on the data lines
(bus). So, the FPGA needs to do something similar; this is called a memory
controller. The timing of the memory controller must match the specs of
the SRAM chip. There may be existing IP for Virtex that already does this.
Perhaps Xilinx's CoreGen creates one (look in ISE). Your VHDL "code" then
uses the memory controller to communicate with the SRAM.
HTH
-Dave Pollum