On Fri, 3 Jul 2009 10:44:18 -0700 (PDT), Walter wrote:

> where is the "extra" signal ?
>TRIG2(x) must be directly connected to FFx;

I agree that there is no new hardware.

In the original post, steve wrote:

> TRIG2(31 downto ????) => fifo_cntl_cs ,

In other words, TRIG2() is not a signal in
his design; it's a port on the ChipScope
instance. So it's impossible to write what
you suggested; it's necessary to declare
an additional signal, use the three assignments
to put the appropriate values on that signal,
and then attach that signal to the ChipScope
port.

Nothing more than that: you need to declare
a suitable signal.
--
Jonathan Bromley, Consultant

DOULOS - Developing Design Know-how
VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services

Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK
[email protected]
http://www.MYCOMPANY.com

The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.