steve escribió:
> On Fri, 3 Jul 2009 16:55:47 +0800, Jonathan Bromley wrote
> (in article <[email protected]>):
>
>> On Fri, 3 Jul 2009 09:19:32 +0800, steve wrote:
>>
>>> BUT I have the following user enumerated types
>>>
>>> type FIFO_CNTL_SM_TYPE is (IDLE, RD_REQ, WR_REQ);
>>> signal fifo_cntl_cs : FIFO_CNTL_SM_TYPE;
>>>
>>> how do i mask this damned thing into chipscope, I just get errors about the
>>> types not matching,.
>>>
>>> TRIG2(31 downto ????) => fifo_cntl_cs ,
>> You need a conversion function.
>>
>> TRIG2(31 downto 29) => to_slv(fifo_cntl_cs),
>>
>> You don't want to introduce any additional logic if you
>> can avoid it, so it makes sense for the conversion
>> function to match the internal encoding that XST has
>> created - see Mike's post.
>>
>> In practice that's likely to be one-hot. So you could do
>> something like this in which each output represents one
>> state. It has the advantage that it won't
>> need to be rewritten if you add or change state names:
>>
>> function to_slv(code: FIFO_CNTL_SM_TYPE)
>> return std_logic_vector
>> is
>> constant LAST: integer :=
>> FIFO_CNTL_SM_TYPE'POS(FIFO_CNTL_SM_TYPE'HIGH);
>> variable result: std_logic_vector(0 to LAST);
>> begin
>> result := (others => '0');
>> result(FIFO_CNTL_SM_TYPE'POS(code)) := '1';
>> return result;
>> end;
>>
>> If you're short of pins on the ChipScope, you could
>> simply convert the integer FIFO_CNTL_SM_TYPE'POS(code)
>> to a std_logic_vector and put that out instead.
>>
>> XST is happy with the 'POS and 'HIGH attributes; I'm
>> not sure it will be OK in all synthesis tools,
>> although there's really no excuse for it not being.
>>
>> Do be aware that adding any such decoder, to observe
>> an enumerated signal, may change the optimization
>> so that the enumeration is encoded differently.
>>
>
> Hi Jonathan,
>
> Thanks for your concise description, it's exactly the guidance I needed.
> Being new to FPGA's I did not realize how gash these tools were.
>
> As regards , changing the logic/ optimization, I'm already aware of that.
> when I try and put my chipscope external to my user_logic and probe
> internally, sometimes the stuff is accessible , other times it disappears, I
> keep looking to see if paul Daniels is behind me..
>
> Like I say these tools and systems are gash, good job Xilinx would never
> dare charging for them. ;-)
>
> Just trying this......
> It looks like it will not work, after adding in the library , it compiles
> fine, but as soon as it links up to chipscope....
> to_slv(xxx)
>
> FATAL_ERROR:Xst:Portability/export/Port_Main.h:143:1.17 - This application
> has discovered an exceptional condition from which it cannot recover.
> Process will terminate. For technical support on this issue, please open a
> WebCase with this project attached at http://www.xilinx.com/support.
>
>
>
> Steve
>
>
>

With a simple SM you can use a simple approach,

TRIGs(31) <= '1' WHEN fifo_cntl_cs = IDLE ELSE '0';
TRIGs(30) <= '1' WHEN fifo_cntl_cs = RD_REQ ELSE '0';
TRIGs(29) <= '1' WHEN fifo_cntl_cs = WR_REQ ELSE '0';

If XST use one-hot encoding this code are only connections.

Walter,