On Fri, 3 Jul 2009 12:31:13 +0800, Mike Treseler wrote
(in article <[email protected]>):

> steve wrote:
>
>> Then I break my signals out and mask into chipscope (all is well with the
>> world for 90% of my signals).
>> BUT I have the following user enumerated types
>>
>> type FIFO_CNTL_SM_TYPE is (IDLE, RD_REQ, WR_REQ);
>> signal fifo_cntl_ns : FIFO_CNTL_SM_TYPE;
>> signal fifo_cntl_cs : FIFO_CNTL_SM_TYPE;
>>
>> how do i mask this damned thing into chipscope, I just get errors about the
>> types not matching,.
>
> The synthesis report has the state encodings.
> Next time, try vhdl simulation, and you can use the enum names directly.
>
> -- Mike Treseler

Hi Mike,

I don't want to simulate it , because i have a 'double clocking' bug that
does not show up in simulation, this has to be a hardware probe, into
User_logic,.
These signals do not show up due to them being optimized out.

We are talking about direct injection of the chipscope core into the user
logic, not it sitting externally.