Hi,
I'm new to FPGA design but I have a minor issue with chipscope .


To get access 'inside' the user core i use 'core generator' followed by the
usual incantations of sticking the pre-generated deffs at the start of the
user_logic. (who thought up this half assed system?)

Then I break my signals out and mask into chipscope (all is well with the
world for 90% of my signals).

BUT I have the following user enumerated types

type FIFO_CNTL_SM_TYPE is (IDLE, RD_REQ, WR_REQ);


signal fifo_cntl_ns : FIFO_CNTL_SM_TYPE;

signal fifo_cntl_cs : FIFO_CNTL_SM_TYPE;

how do i mask this damned thing into chipscope, I just get errors about the
types not matching,.

TRIG2(31 downto ????) => fifo_cntl_cs ,

Thanks

steve