Dave <[email protected]> wrote:

>On Jul 1, 9:40=A0am, Sharanbr <sharan.basa...@gmail.com> wrote:
>> On Jul 1, 3:05 pm, "Symon" <symon_bre...@hotmail.com> wrote:
>>
>> >http://www.xilinx.com/itp/xilinx7/bo...gd0140_101.htm...
>>
>> Thanks, but I was not asking about the setting up the constraints for
>> fpga pinouts, it was a larger question.
>> How do I ensure that I have got a fairly accurate pinout (assuming
>> meeting timing is not an issue) when
>> the design is still under development. Do people create dummy FPGA top
>> and use special tools that only
>> check the validity of the pinouts wrt to the selected device?
>>
>> Look at it this way - people in S/W world exchange information about
>> each other's module
>> by providing the class prototypes and this happens much before the
>> code has been developed.
>>
>> Regards,
>
>You should look at the datasheet and user guide for the device you're
>using, and understand the functionality of the different types of pins
>it has. Then, you can start deciding which pins can go where. Board
>layout concerns and I/O standards come into play as well.

Indeed, but you may still encounter surpises that are not in the
datasheet but can be found in appnotes. For instance: Xilinx has fast
clock sharing between IOBs on Spartan3 devices. These only work for
the top and botton IOBs, not the IOBs on the side. Also, many IOBs
share clock inputs. You can't use 2 different clocks for
inputs/outputs which share those clock lines.

--
Failure does not prove something is impossible, failure simply
indicates you are not using the right tools...
"If it doesn't fit, use a bigger hammer!"
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