On Jul 1, 3:05 pm, "Symon" <symon_bre...@hotmail.com> wrote:
> http://www.xilinx.com/itp/xilinx7/bo...gd0140_101.htm...

Thanks, but I was not asking about the setting up the constraints for
fpga pinouts, it was a larger question.
How do I ensure that I have got a fairly accurate pinout (assuming
meeting timing is not an issue) when
the design is still under development. Do people create dummy FPGA top
and use special tools that only
check the validity of the pinouts wrt to the selected device?

Look at it this way - people in S/W world exchange information about
each other's module
by providing the class prototypes and this happens much before the
code has been developed.

Regards,