>westocl <cweston_@hotmail.com> wrote:
>(big snip)
>
>>>>>> It seems thats exactly the case i will have... What i want to d
is
>>>>>> analagous to having 128 antennas and a situation where i have to
>>>> take the FFT for each antenna. So some kind of rotary switch
>>>> gives me the new antenna input data at every sample...
>>>> and will keep spinning.
>
>(snip)
>
>> I dont mean to sound allusive... I was jut saying that is how you ca
look
>> at the processing i am trying to do.. constantly having differnt block
of
>> data in which to process.
>
>In an FPGA one should be able to do a pipelined parallel implementation,
>with one result (full FFT output) per clock cycle, maybe 3 log2(N)
>clock cycle latency. As you don't say how but your budget is,
>it is hard to say. FPGAs are getting larger pretty fast, though.
>
>-- glen


hmmmm...

Thanks for the info. I can stomach the latency. I think this is what i
going to have to take a look at as long as i get the thru put.

Im not exactly sure of my budget as of yet, im just looking into if what
want to do is even possible with todays devices.