Benjamin Couillard wrote:

> However, when I synthesize "gadgets.vhd", ISE infers the 4 1024x20 bit
> dual-port ram in distributed logic instead of using 8 block rams. I
> have enough block rams in my device for the instantiation so it's not
> some kind of fallback plan by ISE synthesis.

Maybe there are not enough routes to
wire up the 8 block rams.
To find out, do an RTL synthesis and look at the RTL viewer.
That should ignore routing concerns.

> What's even weirder is
> that when I add the "keep_hierarchy" attribute in "widget.vhd", ISE
> will synthesize "gagdets.vhd" with 8 block rams instead of
> synthesizing it with 4 1024x20bit distributed logic ram.

That might be the right answer.
You have given synthesis the hint that saving LUTs is more
important than than saving block ram.


-- Mike Treseler