Hi,

I have a problem with dual-port ram inference. I have a module called
"dual_port_ram.vhd" that I use to infer a dual port ram. This file is
based on Xilinx template and it works well almost everytime.

My problem is the following, I have a module called "widget.vhd" that
instantiates a 1024x20 bit dual-port ram. When I synthesize
widget.vhd, I see that ISE correctly inferred the dual-port ram with
2 block rams.

I have another VHDL module called "gadgets.vhd" that instantiates 4
"widget.vhd" components. We should expect ISE to synthesize
"gagdets.vhd" with 8 block rams.

However, when I synthesize "gadgets.vhd", ISE infers the 4 1024x20 bit
dual-port ram in distributed logic instead of using 8 block rams. I
have enough block rams in my device for the instantiation so it's not
some kind of fallback plan by ISE synthesis. What's even weirder is
that when I add the "keep_hierarchy" attribute in "widget.vhd", ISE
will synthesize "gagdets.vhd" with 8 block rams instead of
synthesizing it with 4 1024x20bit distributed logic ram.

Does anyone here have some kind of explanation?

I use ISE 11.1 with resource sharing disabled.

Best regards

Benjamin