On Sun, 28 Jun 2009 19:48:33 -0700 (PDT), vcar <[email protected]> wrote:

>Since there is async FIFO which will handle the async clock domain
>problem, I think my design should have two unrelated clocks, not the
>related clocks. And all I need to do is to add false path on the
>crossing paths between clock A & clock B. Am I right?

I think so.

If you tell the STA tool that the two clocks are unrelated
(different clock groups) then it should automatically cut
all paths between the two clock domains; there should be
no need to set false paths.

You DO need false paths if the two clocks really are
related, so that some paths need to be timed, but your
FIFO (or whatever) removes the need for STA on
certain paths between the two clock domains.

Which STA tool are you using?
--
Jonathan Bromley, Consultant

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