There is the details information about my design for your better
understanding.

The async FIFO is common FIFO, not the first-word fall-through FIFO.

The Clock A and Clock B are generated by one clock source but from
different PLL/DCM. So ISE will auto relate the two clocks as related
clocks. All the signals in my design crossing clock A and clock B are
passing through async FIFO like the one I listed
(addr_cntrl_fifo_inst).

Since there is async FIFO which will handle the async clock domain
problem, I think my design should have two unrelated clocks, not the
related clocks. And all I need to do is to add false path on the
crossing paths between clock A & clock B. Am I right?