On Jun 28, 3:21*am, vcar <hi...@163.com> wrote:
> The FIFO(addr_cntrl_fifo_inst) has two completely irrelevant clocks,
> say Clock A(trn_clk_c) and Clock B(DDR2_CLK0). The frequency of Clock
> A is 250MHz(Period: 4ns), and Clock B is 266MHz(Period: 3.75ns). Now
> the problem comes when performing STA. The Timing Analyzer reports
> that:
>
> Slack: *-10.394ns (requirement - (data path - clock path skew +
> uncertainty))
> * Source: addr_cntrl_fifo_inst/BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM8_RAMC
> (RAM)
> * Destination: addr_cntrl_fifo_inst/BU2/U0/grf.rf/mem/gdm.dm/dout_i_23
> (FF)
> * Requirement: * * * * 0.250ns
> * Data Path Delay: * * *2.008ns (Levels of Logic = 0)
> * Clock Path Skew: * * *-8.259ns (3.005 - 11.264)
> * Source Clock: * * * *trn_clk_c rising at 56.000ns
> * Destination Clock: * *DDR2_CLK0 rising at 56.250ns
>
> For certain path crossing the different clock domains, the auto
> constraints turned out to be 0.25ns (4ns – 3.75ns). This is impossible
> to achieve.
>
> What should I do to pass the STA?
The timing delay between the rising edges of 250 and 266 MHz is not
limited to 250 ps. (You got that false impression from the rounding
off to 3.75 ns) In reality, there is no lower limit at all, down to
the fractional femtoseconds. That is what makes the control of Full
and Empty flags so challenging.
Peter Alfke, Xilinx