vcar,

I suspect this cross-domain path is the "first-word fall-through"
path: when you write the first word in the -empty- FIFO, it
immediately becomes available on the read port. In such, this path is
real. (With two clocks running at 4ns and 3.75ns, the smallest
distance between two edges is indeed .250ns*in each direction)

However, as a designer, if you know that this will never be exercised,
you need to declare it as a false path. In your case, you probably
should declare false paths between the two clocks (two constraints to
cover each direction), which will cover all paths crossing from one
clock to the other.

- gael