On Jun 26, 12:29 pm, "Antti.Luk...@googlemail.com"
<Antti.Luk...@googlemail.com> wrote:
> On Jun 26, 7:04 pm, Prevailing over Technology <steve.kn...@prevailing-
>
> technology.com> wrote:
> > On Jun 24, 12:14 pm, Antti <Antti.Luk...@googlemail.com> wrote:
>
> > > Bitstreams must not contain a sync word followed by all 1’s. This
> > > condition might
> > > cause damage to the device.
>
> > > Is this an feature or bug? should this go into ERRATA and be fixed
> > > ASAP??
>
> > > Antti
>
> > Hmm, I put this in the same category as a warning stating "DO NOT
> > CRAWL ACROSS BROKEN GLASS."

I see it more as a matter of "warning, and don't blame us if...". I'm
sure this doesn't happen often and when it does it is not in any way
intentional or even inadvertent as in, "I didn't think to prevent
that...". I can only think this would be a real fluke, but if your
$1000 chip fries because of such a fluke, someone is going to ask you
a few questions. But then I guess there are no $1000 Spartans, eh?

BTW, aren't you the guy I owe a punch in the nose... er, I mean a pint
of beer? I think you told me that Xilinx "was committed to supporting
partial reconfiguration in the Spartan 3 devices". That wouldn't be
why you fled
Xilinx would it? ;^)


> > What are the odds of "accidentally" sending a sync. word followed by a
> > few million '1' bits? I'm sure that someone must have done it, hence
> > the errata notice. I'm not sure this would be worth a $1M mask spin
> > to fix (unless there are more important issues as well).
>
> > You can damage lots of semi's by misprogramming them. Have the
> > outputs from two interface devices fight on a bus and just watch the
> > gladiatorial fun!
>
> > -- Steve Knapp
> > Prevailing Technology, Inc.
> > www.prevailing-technology.cm
>
> its not that, only 11's
> you did not read all the fine print
>
> scenarion 1:
> start programming, erase, write sync written, POWER OFF, POWER ON FPGA
> ---> PUFFFF BLOW UP
>
> the above is not 1:MIO odds case or is it?
>
> now, i did include partial info, not only 11111 but also "just bad"
> bit file can damage
> i mean bit files that are INVALID, without proper CRC and trailer
>
> and this seems to be so SEVERE and common to happen, that xilinx
> issued special case HOW TO WRITE FLASH
> (in order to prevent blow up)

I was with you up to this point. "so SEVERE"??? That is a matter of
damned if they do and damned if they don't. The fact that Xilinx has
pointed out a flaw and even taken steps to help users prevent the
inadvertent misuse of the parts certainly shouldn't be used against
them. There has always been the possibility of a bad bit stream
getting past the security logic and doing damage to a chip. Ed's post
above seems to be saying that the reports of the Spartan-6's death has
been greatly exaggerated.


> so from Xilinx docs for S-6
>
> procedure for writing nv memories for S-6
> ERASE
> skip over sync (do not write it), WRITE the bitstream
> seek back, write SYNC
>
> for any other FPGA except S-6 this like procedure for configuration
> memory is not required or recommended
>
> ASFAIK at least
>
> of course it is possible to write KNOWN BLOW UP MY FPGA bitstream, but
> those would be
> valid bitstreams that will overstress the silicon, but INVALID
> bitstreams (that should not release
> the FPGA to be functional) should not damage the FPGA...

How does the chip know a valid bitstream from an invalid one? There
are always bitstreams that the logic can't see as invalid, good
checksum but bad configuration bits.

Rick