On Jun 26, 8:28*pm, glen herrmannsfeldt <g...@ugcs.caltech.edu> wrote:
> Antti.Luk...@googlemail.com <Antti.Luk...@googlemail.com> wrote:
>
> (big snip)
>
> < scenarion 1:
> < start programming, erase, write sync written, POWER OFF, POWER ON FPGA
> < ---> PUFFFF BLOW UP
>
> < the above is not 1:MIO odds case or is it?
>
> < now, i did include partial info, not only 11111 but also "just bad"
> < bit file can damage
> < i mean bit files that are INVALID, without proper CRC and trailer
>
> < and this seems to be so SEVERE and common to happen, that xilinx
> < issued special case HOW TO WRITE FLASH
> < (in order to prevent blow up)
>
> I had thought that previous FPGA families (I might be remembering
> XC4000 series) didn't exit reconfiguration mode until a valid CRC
> was seen. *That would make it unlikely that a random or incomplete
> bit stream would cause damage. *It seems that isn't the case anymore.
>
> -- glen

yes, ASFAIK all FPGA's except Spartan-6 remain in CONFIG mode
until valid CRC and post-amble...

well, i think it all is really ES errata
but for some reason there is no errata sheet available, and it is
described in regular datasheet

Antti