[email protected] <[email protected]> wrote:
(big snip)

< scenarion 1:
< start programming, erase, write sync written, POWER OFF, POWER ON FPGA
< ---> PUFFFF BLOW UP

< the above is not 1:MIO odds case or is it?

< now, i did include partial info, not only 11111 but also "just bad"
< bit file can damage
< i mean bit files that are INVALID, without proper CRC and trailer

< and this seems to be so SEVERE and common to happen, that xilinx
< issued special case HOW TO WRITE FLASH
< (in order to prevent blow up)

I had thought that previous FPGA families (I might be remembering
XC4000 series) didn't exit reconfiguration mode until a valid CRC
was seen. That would make it unlikely that a random or incomplete
bit stream would cause damage. It seems that isn't the case anymore.

-- glen