On Jun 26, 7:04*pm, Prevailing over Technology <steve.kn...@prevailing-
technology.com> wrote:
> On Jun 24, 12:14*pm, Antti <Antti.Luk...@googlemail.com> wrote:
>
> > Bitstreams must not contain a sync word followed by all 1’s. This
> > condition might
> > cause damage to the device.
>
> > Is this an feature or bug? should this go into ERRATA and be fixed
> > ASAP??
>
> > Antti
>
> Hmm, I put this in the same category as a warning stating "DO NOT
> CRAWL ACROSS BROKEN GLASS."
>
> What are the odds of "accidentally" sending a sync. word followed by a
> few million '1' bits? *I'm sure that someone must have done it, hence
> the errata notice. *I'm not sure this would be worth a $1M mask spin
> to fix (unless there are more important issues as well).
>
> You can damage lots of semi's by misprogramming them. *Have the
> outputs from two interface devices fight on a bus and just watch the
> gladiatorial fun!
>
> -- Steve Knapp
> * *Prevailing Technology, Inc.
> * *www.prevailing-technology.cm

its not that, only 11's
you did not read all the fine print

scenarion 1:
start programming, erase, write sync written, POWER OFF, POWER ON FPGA
---> PUFFFF BLOW UP

the above is not 1:MIO odds case or is it?

now, i did include partial info, not only 11111 but also "just bad"
bit file can damage
i mean bit files that are INVALID, without proper CRC and trailer

and this seems to be so SEVERE and common to happen, that xilinx
issued special case HOW TO WRITE FLASH
(in order to prevent blow up)

so from Xilinx docs for S-6

procedure for writing nv memories for S-6
ERASE
skip over sync (do not write it), WRITE the bitstream
seek back, write SYNC

for any other FPGA except S-6 this like procedure for configuration
memory is not required or recommended

ASFAIK at least

of course it is possible to write KNOWN BLOW UP MY FPGA bitstream, but
those would be
valid bitstreams that will overstress the silicon, but INVALID
bitstreams (that should not release
the FPGA to be functional) should not damage the FPGA...

imho


Antti