On Mon, 22 Jun 2009 10:46:51 -0700 (PDT), Test01 <[email protected]>
wrote:

>On Jun 22, 11:52*am, Muzaffer Kal <k...@dspia.com> wrote:
>This is a single ended signal running at 32KHz. It is a free running
>clock running at 32KHz.
>
>> On Mon, 22 Jun 2009 09:21:22 -0700 (PDT), Test01 <cpan...@yahoo.com>
>> wrote:
>>
>> >I have a device that require a free running clock with 0.5V DC offset
>> >and 500mv swing. *(0.25V VIL and 0.75V VIH). * I am using Spartan3
>> >1000 FPGA and all the outputs are connected to 3.3V bank.

You should be able to make it work with a %1 500+100 ohm voltage
divider at the output of your 3.3V IO which puts your VOHmin around
0.5V. If your clock input capacitance is too high and you get slew
rate issues, you can add a transistor driver.
-
Muzaffer Kal

DSPIA INC.
ASIC/FPGA Design Services

http://www.dspia.com