On Jun 22, 11:52*am, Muzaffer Kal <k...@dspia.com> wrote:
This is a single ended signal running at 32KHz. It is a free running
clock running at 32KHz.

> On Mon, 22 Jun 2009 09:21:22 -0700 (PDT), Test01 <cpan...@yahoo.com>
> wrote:
>
> >I have a device that require a free running clock with 0.5V DC offset
> >and 500mv swing. *(0.25V VIL and 0.75V VIH). * I am using Spartan3
> >1000 FPGA and all the outputs are connected to 3.3V bank.
>
> Is this differential or single-ended? And what frequency?
> ---
> Muzaffer Kal
>
> DSPIA INC.
> ASIC/FPGA Design Serviceshttp://www.dspia.com