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Old 06-22-2009, 06:21 PM
Test01
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Default Question on FPGA driver

I have a device that require a free running clock with 0.5V DC offset
and 500mv swing. (0.25V VIL and 0.75V VIH). I am using Spartan3
1000 FPGA and all the outputs are connected to 3.3V bank.

Your ideas are most welcome.

Thanks.

CP
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