I actually just asked someone in my team to check and she confirmed
that indeed (it was a .13 design) the interconnect delays are there,
which does make sense if you have a net with a fanout > 1 and the
different branches are very unbalanced.

I need to doublecheck that the 65nm devices do have interconnect too.

At the same time I think that Muzaffer is right: DC cannot estimate
wire length, so it does not make sense to add interconnects there.
It just lumps all the delay at the output of the driving cell.

We need to check on Solvnet, but alas I have the username/pwd on the
work computer. I'll try later if I power the laptop on

Marco