On Fri, 19 Jun 2009 16:59:13 -0700 (PDT)
[email protected] wrote:

> Rob, John thanks for reply.
>
>
> >> 2. R => not R, S => not S
>
>
> That's the point.
> Your suggestion would infer an inverter realized in a LUT.
> I don't want to infer extra inverter logic in the CLB. I want the
> inverter for free.
>

That's why there's a synthesis tool that's able to perform
optimization. Last I checked, if you go back in to the FPGA Editor
and look in on what you've got, you'll find that XST will very
happily have collapsed those inverters into the free ones built into
the slice.

You seem to be of the opinion that it's necessary for you to outsmart
the synthesis tools. As I said earlier, it's really rarely the case.
If you code:

process(clk, r, s)
begin
if (r = '1') then
q <= '0';
elsif (s = '1') then
q <= '1';
elseif rising_edge(clk) then
q <= d;
end if;
end process;

You'll find that the synthesis tool still gives you exactly what you
wanted, without you having to slog through unnecessary direct
instatiation. The people telling you that it doesn't work haven't updated their opinions since the mid 1990s.

--
Rob Gaddi, Highland Technology
Email address is currently out of order