On Fri, 19 Jun 2009 10:25:01 -0700 (PDT), Arpan <[email protected]>
wrote:
>1) Post synthesis, I expected the wire load models to have some effect
>on the INTERCONNECT delays. My problem is that in the SDF file DC
>generates all interconnect delays come as 0s. I am confused as to why
>this should happen?

This happens because SDF files are not a representation of a netlist
but representation of delay. When delay is calculated one needs to
know all the pin load plus all the wire load a cell output sees and
this is calculated by the extractor and the delay is calculated. At
that point there is no separate wire delay anymore. There are few
instances that two pin loads of a cell will see different delay times
because of different routing but the difference is quite slow for
current processes so most of the interconnect delay values are 0.
Personally I have seen interconnect values other than 0 but at 1ps
resolution nothing higher than 10 yet (at 65nm). As chips get bigger
and feature sizes get smaller this may change but one also has to
remember that we like to keep connectivity local so most delay
differences because of routing will be quite small indeed.
--
Muzaffer Kal

DSPIA INC.
ASIC/FPGA Design Services

http://www.dspia.com