On Jun 19, 10:49*am, Rob Gaddi <rga...@technologyhighland.com> wrote:
> On Fri, 19 Jun 2009 09:50:27 -0700 (PDT)
>
>
>
> len...@gmx.de wrote:
> > Hi,
>
> > I have to instantiate (not inference) two FDRSE elements in my VHDL-
> > Code.
>
> > FDRSE1 should have active-high set/reset.
> > FDRSE2 should have active-low *set/reset.
>
> > This is the instantiation code from the Libraries Guide:
>
> > FDRSE_inst : FDRSE
> > generic map (INIT => '0') -- Initial value of register ('0' or '1')
> > port map (
> > * * * * * * * * * Q * *=> Q, * * *-- Dataoutput
> > * * * * * * * * * C * *=> C, * * *-- Clock input
> > * * * * * * * * * CE => CE, * *-- Clock enable input
> > * * * * * * * * * D * => D, * * *-- Data input
> > * * * * * * * * * R * => R, * * *-- Synchronous reset input
> > * * * * * * * * * S * => S * * * -- Synchronous set input
> > );
>
> > In this instantiation code, there is no possibility to configure the
> > set/reset polarity.
>
> > My two questions are:
>
> > 1. How to instantiate a FDRSE with active-high set/reset
> > 2. How to instantiate a FDRSE with active-low *set/reset
>
> > Thanks in advance,
> > Mark Lenz
>
> 1. You just did.
> 2. R => not R, S => not S
>
> Out of curiosity, why would you need to be directly instantiating
> flops? *I've found very few situations where that's actually the right
> answer (ripple counters, etc).
>
> --
> Rob Gaddi, Highland Technology
> Email address is currently out of order

I believe XST will not directly infer DDR output flops. At least it
didn't used to be
able to do this. I've always had to instantiate DDR output flops.

John Providenza