On Jun 19, 8:19 am, hairyotter <marco.br...@gmail.com> wrote:
> Hi Arpan.
>
> First of all, the default value in the specify block is just a
> placeholder.
> That is meant to be replaced by the sdf.
>
> What dc is doing is:
>
> - calculate the load seen by each cell. This will be the actual C of
> all the input pins being fanout by the driver, plus an estimation of
> R, C due to the net. The amount will come from the wireload model
> tables, if the library has them (in 90nm and smaller this is really a
> useless approximation)
> - use the library files to calculate, based on the load, what will be
> the delay of the cell
>
> I have rarely seen (at least in the flow my company uses) interconnect
> delays used.
> What really is considered important is the delay on the cell only.
>
> I will repeat here the comment I made on the other post: because of
> the huge inaccuracy of the wireload models, the estimation of the net
> length, R, C, other couplings is ridiculous.
>
> In every technology younger than .13 you'll usually get results way
> too optimistic, unless you have small designs.

Hi Marco,
Thank you very much for the response. Couple of questions for you,
note that I am not trying to generate SDF using DC post synthesis from
the perspective of creating a new flow. This is more an academic
pursuit at my end. I hope your response helps in clarifying my
doubts:
1) Post synthesis, I expected the wire load models to have some effect
on the INTERCONNECT delays. My problem is that in the SDF file DC
generates all interconnect delays come as 0s. I am confused as to why
this should happen? I think that you agreed with me on the non-zero
interconnect delay part, the issue is the accuracy of the WLMs.
2) What steps should I take to generate an SDF file in DC that has non-
zero interconnect delays? Any specific command or options would be
very appreciated.

Once again, I look forward communicating with you.

Best Regards,
Arpan