Hi,

I have to instantiate (not inference) two FDRSE elements in my VHDL-
Code.

FDRSE1 should have active-high set/reset.
FDRSE2 should have active-low set/reset.

This is the instantiation code from the Libraries Guide:

FDRSE_inst : FDRSE
generic map (INIT => '0') -- Initial value of register ('0' or '1')
port map (
Q => Q, -- Data output
C => C, -- Clock input
CE => CE, -- Clock enable input
D => D, -- Data input
R => R, -- Synchronous reset input
S => S -- Synchronous set input
);

In this instantiation code, there is no possibility to configure the
set/reset polarity.

My two questions are:

1. How to instantiate a FDRSE with active-high set/reset
2. How to instantiate a FDRSE with active-low set/reset

Thanks in advance,
Mark Lenz