Hi Arpan.

First of all, the default value in the specify block is just a
placeholder.
That is meant to be replaced by the sdf.

What dc is doing is:

- calculate the load seen by each cell. This will be the actual C of
all the input pins being fanout by the driver, plus an estimation of
R, C due to the net. The amount will come from the wireload model
tables, if the library has them (in 90nm and smaller this is really a
useless approximation)
- use the library files to calculate, based on the load, what will be
the delay of the cell

I have rarely seen (at least in the flow my company uses) interconnect
delays used.
What really is considered important is the delay on the cell only.

I will repeat here the comment I made on the other post: because of
the huge inaccuracy of the wireload models, the estimation of the net
length, R, C, other couplings is ridiculous.

In every technology younger than .13 you'll usually get results way
too optimistic, unless you have small designs.