Muzaffer Kal <[email protected]> wrote:
(snip)
< This would even work within an
< ASIC flow for ROMs let alone in an FPGA flow where there is really no
< uninitialized memory and all the contents of all memories (RAM & ROM
< (which actually doesn't exist in an FPGA)) can be loaded to a bit file
< to be downloaded to the FPGA. In that case this makes perfect sense.

I believe that earlier FPGA families wouldn't guarantee the
ability to initialize RAM. That is, that write enable stay inactive
at the appropriate time. As I understand it, many now allow
for initialized RAM. ROM doesn't have write enable, so that
problem doesn't appear.

-- glen