Dear SI gurus -
On single-rank DDR3 dimms - both RDIMMs and UDIMMs - the unused pair of
clocks CK1/CK1# is terminated by a 75-Ohm resistor across the pair. This is
per JEDEC specs.

Does this require that these clocks are routed as 75-Ohm differential on the
mother board? Has anyone see problems arise if on a motherboard they are
routed as 100-Ohm differencial (aka loosely coupled or uncoupled)?

Thanks.
Vadim


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