On May 29, 12:14*am, glen herrmannsfeldt <g...@ugcs.caltech.edu>
wrote:
> In comp.arch.fpga Jake7 <evgen...@gmail.com> wrote:
> (snip, I wrote)
>
> <> Note that Xilinx FPGAs can do 16 bits of LFSR in one SRL16,
> <> which takes up very little space. ?You could easily generate
> <> many of them, also wider than 16 bits. ?
>
> < That's true. I didn't want the tools to generate FPGA-specific code.
>
> It seems that ISE is good at finding shift registers.
> I don't know exactly what ISE find or doesn't find, but it
> seems that the difference is efficient use of space.
>
> -- glen

Glen,

I observe that Xilinx ISE synthesizes shift registers (SRL16 or SRL32)
if the FFs don't have a reset, like this code:

always @(posedge clk) begin
reg_q2 <= reg_q1;
reg_q3 <= reg_q2;
end

So if your CRC/Scrambler/LFSR code doesn't have a reset, it's going to
be synthesized in the most compact way. The downside is that it would
take more effort to reset such a circuit. For example shift 0 through
the SRLs.

Evgeni