In comp.arch.fpga Jake7 <evgenist@gmail.com> wrote:
(snip, I wrote)

<> Note that Xilinx FPGAs can do 16 bits of LFSR in one SRL16,
<> which takes up very little space. ?You could easily generate
<> many of them, also wider than 16 bits. ?

< That's true. I didn't want the tools to generate FPGA-specific code.

It seems that ISE is good at finding shift registers.
I don't know exactly what ISE find or doesn't find, but it
seems that the difference is efficient use of space.

-- glen